1. Field of the Invention
The invention relates to the field of memory arrays and more particularly to redundancy circuitry for large scale integrated circuit memories such as EPROMs and flash memory devices.
2. Description of the Relevant Art
A memory array such as a programmable read-only memory array (PROM) or a random access memory array (RAM) generally comprises an array of programmable binary elements arranged in a matrix of rows and columns having addresses associated therewith and decoders coupled thereto. The binary elements in the RAM can be both written into and read out of, whereas the binary elements in the PROM are either permanently or semi-permanently programmed to one of two states such that information stored in the memory can only be read out.
FIG. 1 illustrates an EPROM (Erasable Programmable Read-Only Memory) circuit 10 including an array of floating gate transistors 12 arranged in rows and columns. Each row is coupled to one of word lines WL-1 to WL-n and each column is coupled to one of bit lines BL-1 to BL-m. A word line decoder 13 receives a first group of address signals on an address bus 14 and drives one of word lines WL-1 to WL-n in response thereto, while a bit line decoder 18 receives a second group of address signals on address bus 14 and selects one of bit lines BL-0 to BL-m in response thereto. Bit line decoder 15 drives a group of output lines 17 that are connected to N-channel field effect transistors 20. For any given address, only one of the word lines WL-1 to WL-n is selected by word line decoder 13, and only one of bit lines BL-1 to BL-m is selected by bit line decoder 15. When a particular row of word lines WL-1 to WL-n is selected, each of the corresponding transistors 12 within the selected row provides either a low impedance path to ground (from drain to source) if it is erased (threshold voltage low), or a high impedance path to ground if it is programmed (threshold voltage high).
It should be noted that each transistor 12 within the memory array is referred to as a "cell". It is further appreciated, as known to those skilled in the art, that each of the floating gate transistors 12 can be programmed electrically by applying a high voltage on the drain and the select gate of the device, thus allowing current to flow to the source and resulting in negative charging of the floating gate. Furthermore, for the EPROM circuit 10, the transistors 12 are erased by exposing the memory array to ultraviolet light to thereby electrically neutralize the floating gate. In alternative memory array structures such as flash memory devices or E.sup.2 PROMs (Electrically Erasable Programmable Read-Only Memory), erasing of each memory cell is achieved electronically. When a particular memory cell transistor 12 is programmed, its threshold voltage is high, e.g. above 5 volts. When a particular memory cell transistor 12 is erased, its threshold voltage is low, e.g. from approximately 1 to 2 volts.
Transistors 20 collectively form a circuit referred to as a column select circuit. Included within transistors 20 are transistors 20a-20c having drains coupled to a node 24. The source connections of transistors 20b and 20c are not shown to simplify the illustration, but the sources of transistors 20b and 20c are typically connected to a set of bit line decode transistors such as transistors 20d, 20e and 20f, which in turn are coupled to associated bit lines BL-1 to BL-m. When one column of bit lines BL-1 to BL-m is selected by bit line decoder 15, the pair of corresponding transistors 20 connected to the selected column (bit line) are turned on, therefore selectively coupling those particular transistors 12 to the node 21. For example, for an appropriate predetermined address signal on address bus 14, bit line decoder 15 generates high signals at the gates of transistors 20a and 20d, thereby turning the devices on and causing selection of bit line BL-1.
The selected bit line BL-1 to BL-m coupled through the pair of corresponding transistors 20 to node 21 is biased by a bias circuit 23. Node 21 is further coupled to a first input lead 24 of a sense amplifier 25. When it is desired to read data stored in a selected transistor 12, the voltage at the word line WL-1 to WL-n connecting the control gate of the selected transistor 12 is raised, e.g., to about 5 volts. If the floating gate of the selected transistor 12 is electrically neutral and thus erased, the voltage at input lead 24 goes low when the voltage at the control gate increases and the selected transistor 12 turns on. If the floating gate is negatively charged and thus programmed, the voltage at input lead 24 remains high. Sense amplifier 25 compares the voltage at input lead 24 to a reference voltage V.sub.ref provided by a reference voltage generator 26 and generates therefrom an output signal on the output lead 27 in response thereto. The signal on output lead 27 is communicated via a tri-state buffer 28 to an output pin 29.
Large scale integration techniques have made possible the construction of memory devices having large arrays of binary storage elements such as transistors 12 on a single chip of silicon or other substrate. The immediate advantages of such arrangements are the high cell density and low power requirements. However, in the production of integrated circuit chips, it is not unusual for the yield of flawless chips processed from a silicon wafer to be low, especially during early production runs. For each perfect chip produced, there are a number of chips that are almost perfect, having one or more localized defects which render unusable a single cell or a few closely associated cells or clusters of cells.
As cell density increases, it follows that the likelihood of processing defects also increases. The problem of processing defects has been especially troublesome in the fabrication of matrix memory devices. On one hand, innovations in computer technology have made desirable the production of larger memories, and it is possible to fabricate these larger memories on a single wafer. However, if the error or defect rate is high, the cost of producing the larger memory can be excessive due to defective cells. On the other hand, the cost of producing smaller, individual memory components which then must be interconnected utilizing circuit boards and wiring is also undesirably high. It will be appreciated that the presence of only one defective cell in an otherwise perfect memory array can render useless the entire memory array. Therefore, there is a continuing interest in techniques for improving the yield of perfect arrays, and for repairing or otherwise rendering usable those memory arrays having processing defects.
Many techniques have been advanced for improving yield. For example, error correction codes have been used to correct words read from a memory array in which certain bits of the word are stored in defective cells.
Additionally, defect tolerant memory systems have been disclosed in which an entire redundant row or column of cells is substituted for a selected row or column containing one or more defective cells. One such memory redundancy system employs fusible silicon links which present a low impedance path when intact or a high impedance path when blown and thereby allow defective rows or columns to be bypassed. The memory redundancy system utilizing the fusible link technique however requires that both the memory connections and external connections thereto be rewired such that redundant rows and columns can be coupled into the processing circuitry in place of the defective row and column if the same address is to be retained. This requirement increases mass production costs.
In yet another arrangement, a cell addressable array utilizes a redundant row or column of cells together with a defective word address register and a comparator circuit for disabling a defective row (or column) of cells and replacing it with a redundant row (or column) of cells. For such an arrangement, when the word in the address of a defective cell is requested, the comparator circuitry recognizes the address as corresponding to a defective cell and thereby provides a new address which corresponds to the redundant row which stores the correct word for access. Although such an arrangement is advantageous because the memory does not need rewiring and a physical fuse need not be blown, the access time of the memory is increased due to the comparator circuitry, and in addition, power consumption is increased.
The access time of a large scale integrated circuit memory is the time delay between the time at which the address change occurs or the chip enable active occurs to the time at which valid data from the requested location is provided at an output bus. With advances in scaling and design innovations, the access times for recent memories have been decreasing. EPROM access times typically in the 450 nanoseconds range a few years ago have decreased to less than 100 nanoseconds. The time required for access as a result of prior art redundancy techniques has therefore become significant with respect to the overall access time of the memory.
A memory circuit having a decreased access time and a reduced power consumption is desirable.